The electronics industry has experienced an ever increasing demand for smaller and faster electronic devices which are simultaneously able to support a greater number of increasingly complex and sophisticated functions. Accordingly, there is a continuing trend in the semiconductor industry to manufacture low-cost, high-performance, and low power consumption integrated circuits (ICs). These goals have been achieved in large part by scaling down semiconductor IC dimensions (e.g., minimum feature size) and thereby improving production efficiency and lowering associated costs. Nevertheless, there are physical limits to the density that can be achieved in two dimensions for integrated circuits.
Three-dimensional (3D) stacking of semiconductor devices is one avenue to tackle these issues for further density. Technologies to construct 3D stacked integrated circuits or chips include 3D packaging, parallel 3D integration and monolithic 3D IC technologies. Among these technologies, the monolithic 3D IC technology exhibits the advantages of cost-effective, small area and high heterogeneous integration capability. However, the monolithic 3D IC technology has a critical problem, in which the process of forming the upper layer devices would be harmful to the lower layer devices due to its high thermal budget requirements.